1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a method for manufacturing a one-time electrically programmable read only memory (OTEPROM).
2. Description of the Related Art
As semiconductor production enters the deep sub-micron stage, the dimension of devices is significantly miniaturized. For memory devices, this represents a significant reduction in the size of each memory cell. As the amount of data that needs to be processed and stored in an electronic communication product (such as a computer, a mobile phone, a digital camera or a personal digital assistant) continues to increase, the memory storage capacity required by these electronic communication products increases at an accelerating rate. With the rapid improvement in semiconductor manufacturing techniques, most semiconductor processes are aiming towards increasing the density of devices in a wafer and miniaturizing the size of each device so that overall level of integration can be increased. In other words, there is a great demand for small size but high storage capacity memory devices. How to produce small, highly integrated, high capacity and high quality memory devices is the common goal for all device manufacturers.
According to the difference in read/write function, memory can be simply categorized into read only memory (ROM) and random access memory (RAM). Because the memory messages or data stored in the read only memory will not be deleted even when the power to the device is cut off, this type of memory is also called non-volatile memory.
In general, read only memory can be further divided into erasable programmable read only memory (EPROM), one-time electrically programmable read only memory (OTEPROM), electrically erasable programmable read only memory (EEPROM) and mask read only memory (mask ROM).
The one-time electrically programmable read only memory (OTEPROM) permits the writing of data into the memory after leaving the factory. That is, the data can be written by the user to fit a particular memory environment, which is more convenient to a user.
FIG. 1 is a top view of a conventional OTEPROM. FIG. 2 is a schematic cross-sectional view taken along line A–A′ of the OTEPROM in FIG. 1.
As shown in FIGS. 1 and 2, the OTEPROM includes a memory cell 10 and a memory cell 20. Since the memory cell 10 and the memory cell 20 are structurally the same, only the memory cell 10 is described.
The memory cell 10 mainly includes a substrate 100, a polysilicon floating gate 101, a word line 103, a plurality of gate dielectric layers 104, a plurality of source/drain regions 105, a plurality of device isolation structures 107 and a plurality of spacers 109. The polysilicon floating gate 101 and the word line 103 are disposed on the substrate 100. The gate dielectric layers 104 are disposed between the substrate and the polysilicon floating gate 101 and the word line 103. The source/drain regions 105 are disposed in the substrate 100 adjacent to the sides of the polysilicon floating gate 101 and the word line 103. The device isolation structures 107 are disposed in the substrate 100. The spacers 109 are disposed on the sidewalls of the polysilicon floating gate 101 and the word line 103.
In the process of manufacturing the aforementioned OTEPROM, the polysilicon floating gate 101 is directly patterned using the photolithographic and etching technique. However, photolithographic technique is often limited by the so-called optical limitations. To prevent any misalignment in the photolithographic process or any damages to the polysilicon layer by etching solution in the etching operation when patterning out the polysilicon floating gate 101, a portion of the polysilicon floating gate 101 will extend into the device isolation structure 107. Hence, after the polysilicon floating gate 101 has been patterned, its dimension will be greater than the originally required area (in FIG. 1, ‘a’ is the reserved area). Yet, the reserved area in the aforementioned structure is simply a waste of the substrate area, which is contrary to the current trend in semiconductor fabrication.